The present invention relates generally to charge pump circuits and in particular the present invention relates to an improved low voltage charge pump circuit.
Phase lock loop circuits (PLL) are used to generate an output signal that has the same phase as a reference, or input, signal. The PLL typically includes a phase/frequency detector, a charge pump, loop filter and a controlled oscillator. The charge pump provides output signal(s) that control the oscillator.
One embodiment of a differential charge pump that can be used in a PLL is illustrated in FIG. 1. This charge pump includes differential n-channel transistor pairs M1 and M2, and M3 and M4. Each differential transistor pair has gates coupled to receive differential input voltage. For example, M1 and M2 receive a first differential phase voltages (UP and /UP) and transistors M3 and M4 receive a second differential phase voltage (DOWN and /DOWN). The differential pairs steer current to the output nodes. The output current is determined by Ip and the voltage present at the inputs (Up, /UP, /DOWN, /DOWN). The input signals of the differential circuit control only pull-down currents.
The pump circuitry includes a common mode feedback circuit used to maintain a proper output common mode. That is, the output signals provide a differential signal that changes about a common mode voltage level. In some applications, it is desired to maintain this level in the mid-range of the voltage supply (xcx9cVdd/2).
The common mode feedback circuit includes transistors M5 to M9. During operation of the pull-down transistors (M1-M4), P-channel transistors M5 and M6 steer current to n-channel transistor M9 in response to transistors M1-M4 and any output loading. The current conducted through M9 is used to establish gate voltages for n-channel transistors M7 and M8. The size of the transistors is chosen to establish a predetermined common mode level. If the common mode of the output signals changes, the common mode feedback circuit compensates for the change. For example, if the common mode on the output nodes increases, transistors M7 and M8 will conduct more current to reduce the output node voltage. Likewise, transistors M7 and M8 will decrease current drain from the output nodes if the common mode level is reduced.
The circuit of FIG. 1 is not easily applied to low voltage circuits. That is, the gate-source voltage drops (Vgs) across M5 and M6 in series with M9 may be too great in a low voltage circuit. For example, if Vdd in FIG. 1 is 1.8 volts, the Vgs drop across transistors M5 and M6 is about a threshold voltage, Vt, plus a drain-source saturation voltage (Vsat). Similarly, M9 has a voltage drop of vt+Vsat. If Vt is 0.5 volts and Vsat is 0.1 volts, the common mode will be about 1.2 volts. In a 1.8 volt system, the common mode is substantially greater than the desired 0.9 volt level.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a differential charge pump circuit that can be implemented in a low voltage circuit.
The above-mentioned problems with charge pump circuitry and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a charge pump circuit comprises a differential circuit having input connections to receive first and second complimentary input signal pairs, and first and second output connections provide first and second output signals in response to the first and second complimentary input signal pairs. A common mode feedback circuit is coupled to the output connections. The common mode feedback circuit comprises a first current path to conduct a first current in response to the first output signal, a second current path to conduct a second current in response to the second output signal, and a current mirror circuit coupled to the first and second current paths. The current mirror circuit is coupled to selectively control bias circuitry coupled to the first and second outputs.
In another embodiment, a charge pump circuit comprises a differential circuit comprising, a first pull-down transistor coupled to a first output node, a gate of the first pull-down transistor is coupled to receive a first input voltage signal, and a second pull-down transistor coupled to a second output node, a gate of the second pull-down transistor is coupled to receive a second input voltage signal. The differential circuit further comprises a third pull-down transistor coupled to the first output node, a gate of the third pull-down transistor is coupled to receive a third input voltage signal, and a fourth pull-down transistor coupled to the second output node, a gate of the fourth pull-down transistor is coupled to receive a fourth input voltage signal. A common mode feedback circuit is coupled to the first and second output nodes. The common mode feedback circuit comprises a first current path to conduct a first current (primary current) in response to a voltage on the first output node, the first current path comprising first and second series coupled transistors, a second current path to conduct a second current in response to a voltage on the second output node, the second current path comprising third and fourth series coupled transistors, a first current mirror circuit coupled to replicate the first current, and a second current mirror circuit coupled to replicate the second current (this current may be a multiple of the primary current). The first and second current mirror circuits control bias circuitry coupled to the first and second output nodes.
A differential charge pump circuit is provided, in one embodiment, that comprises first and second differential input connections to receive first and second differential input signal pairs, and first and second output connections to provide a differential output signal having a common mode voltage, wherein the differential charge pump circuit operates with a supply voltage that is less than 2.0 volts and maintains a common mode voltage that is less than 1.0 volts. In another embodiment, the supply voltage that is less than 2.5 volts and maintains a common mode voltage that is less than 1.25 volts.
In yet another embodiment, a phase locked loop circuit comprises a phase-frequency detector circuit, and a differential charge pump circuit coupled to an output of the phase-frequency detector circuit. The differential charge pump circuit has first and second output connections to provide a differential output signal having a common mode voltage, wherein the differential charge pump circuit operates with a supply voltage that is less than 2.0 volts and maintains a common mode voltage that is less than 1.0 volts. A voltage-controlled oscillator is coupled to the differential charge pump circuit to provide a feedback signal to the phase-frequency detector circuit. A loop filter is coupled to the charge pump and the voltage controlled oscillator.
A phase locked loop circuit is provided that comprises a phase-frequency detector circuit, and a differential charge pump circuit coupled to an output of the phase-frequency detector circuit. The differential charge pump circuit has first and second output connections to provide a differential output signal having a common mode voltage. A voltage-controlled oscillator is coupled to the differential charge pump circuit to provide a feedback signal to the phase-frequency detector circuit, and a loop filter is coupled to the charge pump and the voltage controlled oscillator. The differential charge pump circuit comprises a common mode feedback circuit coupled to the first and second output connections. The common mode feedback circuit comprises a first current path to conduct a first current in response to a voltage on the first output connection, a second current path to conduct a second current in response to a voltage on the second output connection, and a current mirror circuit coupled to the first and second current paths, the current mirror circuit is coupled to selectively activate bias circuitry coupled to the first and second outputs.